Main Project Status (06/27/2017 - 19:19:22) | |||
Project File: | myCPUv3.xise | Parser Errors: | No Errors |
Module Name: | Controller | Implementation State: | Synthesized |
Target Device: | xc3s50-5pq208 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 33 | 768 | 4% | |
Number of Slice Flip Flops | 9 | 1536 | 0% | |
Number of 4 input LUTs | 59 | 1536 | 3% | |
Number of bonded IOBs | 50 | 124 | 40% | |
Number of GCLKs | 1 | 8 | 12% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Tue Jun 27 19:18:32 2017 | ||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | Tue Jun 27 20:41:28 2017 |