Main Project Status (06/27/2017 - 19:19:22)
Project File: myCPUv3.xise Parser Errors: No Errors
Module Name: Main Implementation State: Synthesized
Target Device: xc3s50-5pq208
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
11 Warnings (11 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 149 768 19%
Number of Slice Flip Flops 83 1536 5%
Number of 4 input LUTs 282 1536 18%
Number of bonded IOBs 45 124 36%
Number of BRAMs 4 4 100%
Number of GCLKs 1 8 12%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Jun 27 19:19:18 2017011 Warnings (11 new)19 Infos (2 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentTue Jun 27 22:03:37 2017

Date Generated: 07/04/2017 - 16:53:28