Main Project Status (06/27/2017 - 19:19:22)
Project File: myCPUv3.xise Parser Errors: No Errors
Module Name: Controller Implementation State: Synthesized
Target Device: xc3s50-5pq208
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 33 768 4%
Number of Slice Flip Flops 9 1536 0%
Number of 4 input LUTs 59 1536 3%
Number of bonded IOBs 50 124 40%
Number of GCLKs 1 8 12%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Jun 27 19:18:32 2017   
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentTue Jun 27 20:41:28 2017

Date Generated: 06/27/2017 - 20:43:45